1. Field of the Invention
This invention is relating to a method for manufacturing a semiconductor device, particularly to a method for manufacturing, for example, a double diffused MOSFET (referred to hereinafter as a DMOS).
2. Description of the Related Art
A vertical type DMOS by which a low ON resistance and high withstanding voltage can be comparatively easily obtained has been generally used as an element in the construction of, for example, a power MOSFET. In this element, a plurality of unit cell transistors each having a size of several tens of .mu.m are connected in parallel to form one element.
Hereafter, a current method for manufacturing the vertical type DMOS is explained with reference to FIG. 2.
First, as shown in FIG. 2, (a), an N.sup.- -type epitaxial layer 22 is formed on a main surface of an N.sup.+ -type Si substrate 21 by an epitaxial growth process and a gate oxide film 23 consisting of SiO.sub.2 is fabricated by oxidizing a main surface of the N.sup.- -type epitaxial layer 22 with heat. Then, as shown in FIG. 2(b), a polycrystalline silicon layer 24 is deposited on a surface of the gate oxide film 23 by a CVD (Chemical Vapor Deposition) method.
Thereafter, as shown in FIG. 2(c), an opening is provided at a desired region of the polycrystalline silicon layer 24 by an etching method utilizing reactive ions (referred to hereinafter as RIE) and a P-type well region 27 is formed by implanting P-type impurities by ion implantation, using the residual polycrystalline silicon layer 24 as a mask.
A resist 26a is then formed on a desired region in the above opening by a photo etching method, and an N.sup.+ -type diffusion region 28 is formed in the P-type well region 27 by implanting N-type impurities by ion implantation, using the residual polycrystalline silicon layer 24 and the resist 26a as a mask.
Then, as shown in FIG. 2(d), the resist 26a is removed and an insulating layer 25 consisting of SiO.sub.2 is deposited on a whole surface of the device by a CVD method.
Finally, as shown in FIG. 2(e), a resist 26b is formed on a desired region of said insulating layer 25 by photo etching and the insulating layer 25 and the gate oxide film 23 are etched using the resist 26b as a mask, and a line means of, for example, Al (not show), is provided in electrical contact with the P-type well region 27 and N-type diffusion region 28.
The vertical type DMOS thus produced comprises an N.sup.+ -type Si substrate 21 and an N.sup.- -type epitaxial layer 22 as a drain region, an N.sup.+ -type diffusion region 28 as a source region, a polycrystalline silicon layer 24 as a gate electrode and a P-type well region 27 as a channel region.
When the ON resistance of the power MOSFET is reduced, the current drive performance is increased, and thus the size of the device can be reduced. Accordingly, the ON resistance should be made as low as possible, to meet present requirement for minimizing a chip size and therefore, a number of unit cells provided in the same chip size must be increased, to widen a total channel width thereof by minimizing the size of an element thereof, and thus reduce the size of the unit cell.
Especially, a great effect can be obtained when a withstand voltage of less than 100 V is used, as this enables the extent of a contribution of the channel width to the ON resistance to be improved.
As mentioned above, to make the ON resistance low, preferably the size of the unit cell is reduced.
But, in the current method, in each step, for example, when the N.sup.+ -type diffusion region 28 is formed inside the P-type well region 27 as explained in FIG. 2(c) and when the opening is formed in the insulating layer 25 and said gate oxide film 23 to provide an electrical connection among the P-type well region 27, N-type diffusion region 28, and wiring means, a photo etching method is applied to the resists 26a and 26b and thus there is a great possibility that deviations between the position of the glass mask and that of the element will occur, and accordingly, marginal portions of about .+-.3 .mu.m are usually required when designing a unit cell size if a 1:1 projection exposure device is used, and consequently, the minimum size of the unit cell is limited to about 25 to 30 .mu.m.
On the other hand, the unit cell size can be reduced to around 15 to 20 .mu.m by using a reduction projecting exposure device such as a 1:5 Stepper (Direct Stepping on Wafer), but in such a case, a problem arises in that the cost of production of an element will be increased.